1. Field of the Invention
This invention relates to integrated circuit manufacturing and, more particularly, to a method and system for polishing a semiconductor topography in which an acidic liquid substantially free of particulate matter is applied between the semiconductor topography and a surface entrained with abrasive particles.
2. Description of the Related Art
Fabrication of a multi-level integrated circuit involves numerous processing steps. After impurity regions have been formed within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed across the semiconductor topography and connected to the impurity regions. An interlevel dielectric is formed between the interconnect routing and the substrate to isolate the two levels. Contact areas are placed through the dielectric to electrically link the interconnect routing to select impurity regions extending across the substrate. A second level of interconnect routing may be placed across a second level of interlevel dielectric arranged above the first level of interconnect routing. The first and second levels of interconnect routing may be coupled together by contact structures arranged through the second level of interlevel dielectric. Additional levels of interconnect routing and interlevel dielectric may be formed, if desired.
Unfortunately, unwanted surface irregularities (i.e., elevation disparities) occur across the topological surface prior to and after forming a multi-level interconnect structure. For example, a recess may form in the surface of a semiconductor topography during the formation of trench isolation structures within, e.g., a silicon-based substrate. The trench isolation process involves etching a trench within the substrate, followed by chemical-vapor deposition ("CVD") of a dielectric material into the trench and across the substrate to a level spaced above an upper surface of the substrate. Since the dielectric material accumulates at the same rate upon the base of the trench as well as upon the substrate upper surface laterally outside the trench, a recess will occur in the upper surface of the dielectric material above the trench area. If left unattended, such elevational disparities in the surface of a dielectric layer can lead to various problems. For example, when an interconnect layer is placed across a dielectric surface having elevationally raised and recessed regions, step coverage problems may result. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film on horizontal regions. Another problem resulting from elevational disparity occurs when subsequent layers are lithographically patterned from the deposited layer. Demarcation between polymerized or non-polymerized photoresist will skew in a lateral dimension as a result of a change in depth-of-focus depending on whether the photoresist resides in an elevational "hill" or "valley" area.
The concept of utilizing chemical and mechanical abrasion to planarize and remove surface irregularities of a topological surface is well known in industry as chemical-mechanical polishing ("CMP"). As shown in FIG. 1, a typical CMP process involves placing a semiconductor wafer 12 face-down on a polishing pad 14 which is fixedly attached to a rotatable table or platen 16. Elevationally extending features of semiconductor wafer 12 are positioned such that they contact the slurry attributed to the CMP process. The polishing pad may be made of various substances, depending on the material being polished. A popular polishing pad medium comprises polyurethane or polyurethane-impregnated polyester felts. An example of a somewhat hard polishing pad is the IC-1000 type pad commercially available from Rodel Products Corporation. A relatively soft pad is the SUBA 500 type pad, also manufactured by Rodel Products Corporation. During the CMP process, polishing pad 14 and semiconductor wafer 12 may be rotated while a carrier 10 holding wafer 12 applies a downward force F upon polishing pad 14. An abrasive, fluid-based chemical, often referred to as a "slurry", is deposited upon the surface of polishing pad 14 via a conduit 18 positioned typically above the pad. In this manner, the slurry occupies an interface between pad 14 and the surface of wafer 12. The slurry initiates the polishing process by chemically reacting with the surface material being polished. The rotational movement of polishing pad 14 relative to wafer 12 causes abrasive particles entrained within the slurry to physically strip the reacted surface material from wafer 12. The abrasive slurry particles are typically composed of silica, alumina, or ceria. A polishing apparatus for polishing hard and fragile materials is described in U.S. Pat. No. 5,032,203, which is incorporated herein by reference.
Delivery of the slurry must be carefully monitored so as not to unduly accumulate in select regions of the topography. If too much slurry accumulates in a relatively small area, that area may scratch or, in the extreme, polish at an unacceptably high polish rate. A post-CMP cleaning step is required to remove residual slurry particles from the surface of the polished topography. Without adequately removing the slurry, abrasive slurry particles will remain on the semiconductor topography and contaminate that surface. Considering the minute dimensions of integrated circuit topological features, even the tiniest of defect in the semiconductor topography can render the ensuing integrated circuit inoperable. U.S. Pat. No. 5,320,706 (incorporated herein by reference) describes a method for removing slurry particle residue from a wafer surface by polishing the wafer with a pad while a mixture of deionized water and a surfactant is applied to the wafer and pad. Unfortunately, the removal of such slurry particles may be time consuming and costly. Further, some types of cleaning procedures can be detrimental to the semiconductor topography. The slurry waste must also be disposed of and subjected to waste treatment after planarization is complete because of the toxic nature of some of the effluent components. The disposal and waste treatment of the slurry effluent significantly increases the cost of manufacturing the integrated circuit. Various problems associated with CMP are described in "Chemical-mechanical polishing of interlayer dielectric: A review", Ali et al., Solid State Technology, October 1994, pp. 63-68 (incorporated herein by reference).
FIGS. 2, 3 and 4 illustrate the formation of a trench isolation structure within a semiconductor substrate, according to a conventional technique. As shown in FIG. 2, a semiconductor substrate 20 comprising, e.g., lightly doped single crystalline silicon is provided. A silicon nitride ("nitride") layer 24 is arranged across the upper surface of substrate 20. A "pad" oxide layer 22 may be interposed between substrate 20 and nitride layer 24 to reduce inherent stresses between nitride and silicon. As shown, portions of nitride layer 24 and substrate 20 are etched away to define a trench 21 within substrate 20. Turning to FIG. 3, a fill oxide 26 is then CVD deposited into trench 21 to a level spaced above the upper surface of nitride layer 24. Prior to depositing fill oxide 26, a thermally grown oxide liner may be formed at the periphery of trench 21 while nitride layer 24 protects the upper surface of substrate 20 from being oxidized. The resulting upper surface of fill oxide 26 includes a recess 27 arranged above the trench area. A CMP step is then performed to planarize the surface of the semiconductor topography.
As shown in FIG. 4, CMP is applied to the topography of FIG. 3 to remove the topological surface down to a level 28b spaced below the original upper surface 28a of substrate 20. The chemical slurry used to polish the topological surface reacts and therefore removes oxide at a higher rate than nitride. Accordingly, fill oxide 26 is removed to an elevation level below nitride layer 24. It may be difficult to determine the exact amount of time required to remove the upper surface of fill oxide 26 down to a level coplanar with the upper surface of nitride layer 24. Unfortunately, removal of nitride may contaminate the substrate "active areas" beneath nitride layer 24. Ensuing impurity regions implanted into the active regions may not receive an optimal dosage and/or implant profile. In an extreme, implant regions may extend below the base of the fill oxide or above the surface of the fill oxide. In the former instance, current may leak between isolated junction, and in the latter instance, the exposed comers of the junctions may suffer unreasonably low breakdown voltages. Further, a lowered active area resulting from excessive CMP may cause the active area to no longer be a pristine crystalline lattice and thus may include dangling bonds and an irregular grain structure which can provide opportune bond sites and migration pathways to foreign atoms during later processing steps.
The topological surface of fill oxide 26 contains an elevationally recessed region 30 and is not planar in large lateral-area trenches. The slurry chemistry may have contributed to the non-planarity of the surface of fill oxide 26. During the CM N process, the slurry, being a relatively viscous fluid, may have flowed to the elevationally recessed region of the topological surface of fill oxide 26. The slurry thusly placed may have reacted with the surface material at the elevationally recessed region, releasing the surface material from its union with the bulk of fill oxide 26. Further, the polishing pad, being somewhat conformal to the topological surface, may have deformed to the elevationally raised and recessed topography by "bowing" in an arcuate pattern in response to a force being applied thereto. Therefore, deformation in polishing pad planarity may have also contributed to the formation of elevationally recessed region 30 by physically stripping the reacted surface material of fill oxide 26 from the semiconductor topography. Thus, while the removal rate of elevationally raised regions of the semiconductor may have been greater than that of the elevationally recessed region, a significant amount of the elevationally recessed region has, unfortunately, also been removed.
It would therefore be desirable to develop a process for polishing a semiconductor topography without being concerned with unwanted removal of elevationally recessed regions of the material being polished. As such, it is necessary to prevent the CMP polishing fluid from reacting with the elevationally recessed regions of the semiconductor topography. Further, using a substantially rigid polishing pad that does not significantly deform when subjected to pressure would provide for reduced removal of the elevationally recessed regions. A planarization process which selectively removes raised areas faster than recessed areas of the same material, or one material in lieu of another material would also be beneficial. The desired planarization process could be applied to global planarization of an elevationally disparate dielectric or conductive surface, or selective planarization of a dielectric in a trench isolation process or a conductor in a contact-fill (or "plug") process. In instances where a trench isolation structure is to be formed, removal of substrate active areas beneath the nitride layer would be substantially eliminated at times when the fill oxide is being planarized. It would also be beneficial to devise a polish process that does not require the costly removal and treatment of slurry waste. Further, a CMP and/or polish process is needed in which there is less risk of the semiconductor topography being damaged or contaminated by abrasive slurry particles during and/or following CMP.